Conventionally, there has been used a wiring substrate in which a core is disposed at the center thereof and in which conductor layers and insulation layers are laminated alternatingly on the upper surface and on the lower surface of the core, thereby forming respective buildup layers. In the case where a package is formed through mounting of a semiconductor device on such a wiring substrate, in order to stabilize a power-supply voltage to be supplied to the semiconductor device from an external board and to reduce noise, disposition of a capacitor on the package for connection to power-supply lines is desirable. In this case, in order to reduce the wiring distance between the capacitor and the semiconductor device, a wiring substrate in which a capacitor is incorporated is proposed. Such a capacitor-incorporated wiring substrate employs, for example, the following structure: the wiring substrate has an accommodation portion, and a via-array-type capacitor having a plurality of via conductors arranged in an array is accommodated in the accommodation portion (refer to, for example, Patent Document 1).
Generally, in the via-array-type capacitor, via conductors connected to positive-side internal electrode layers and via conductors connected to negative-side internal electrode layers are arranged alternatingly. Thus, it is necessary to form two kinds of electrode patterns on an electrode layer formed on each of the front and back surfaces of the capacitor, for connection to two kinds of via conductors respectively corresponding to the positive side and the negative side. The surface electrode layer of this type of capacitor has, for example, a planar structure shown in FIG. 15. In FIG. 15, there are arranged a plurality of via conductors Va to be connected to the ground, which is on the negative side, and a plurality of via conductors Vb to be connected to a power-supply voltage, which is on the positive side. A negative-side electrode pattern Pa is in the form of a solid pattern and is connected unitarily to the upper ends of a plurality of the via conductors Va, whereas a positive-side electrode pattern Pb is in the form of a plurality of independent constituent patterns connected to the respective upper ends of a plurality of the via conductors Vb. A multilayer laminate portion of the wiring substrate is provided on the surface electrode layer of FIG. 15. In the laminate portion, conductor layers which are patterned in a manner similar to that of the surface electrode layer are laminated. A semiconductor chip, for example, is mounted on the laminate portion. The via conductors Va and Vb are electrically connected to respective pads of the semiconductor chip via a via-conductor group extending through the laminate portion disposed thereabove.